IBM and its Common Platform technology partners Chartered Semiconductor Manufacturing and Samsung Electronics, along with joint-development alliance partners Infineon Technologies AG and Freescale Semiconductor, have signed a series of semiconductor process development and manufacturing agreements. The partners plan to pool their combined expertise and collaborate to design, develop and manufacture advanced technology through 2010.
The joint development agreements between these companies will now include 32-nanometer (nm) bulk complementary metal oxide semiconductor (CMOS) process technologies and joint development of process design kits (PDKs) to support that technology. Building on the success of earlier joint development and manufacturing agreements at 90nm, 65nm and 45nm, alliance partners will be able to produce high-performance, energy-efficient chips at 32nm.
"The industry has recognized the value and importance of the collaborative model in driving robust, cost-effective solutions," said Chia Song Hwee, president and CEO of Chartered. "As we now collaborate on our fourth node under this joint model, we have seen how each company brings unique strengths and expertise to drive a customer-centric offering. The results of our collaboration have served as a platform for providing customers with world-class, flexible sourcing solutions."
IBM, Chartered and Samsung, as Common Platform technology manufacturers, will be able to use the jointly developed 32nm process technology and design kits to synchronize their manufacturing facilities. This helps facilitate the flexibility to produce nearly identical chips for their respective high-volume OEM clients, who require a multi-sourcing model and expect early access to process technology.
The five companies will work together to deliver industry-leading technology for high-performance and low-standby power products through:
- a focus on low cost and minimum complexity while retaining performance leadership
- implementation of new materials such as high-k/metal gate, advanced stress engineering, and extreme low-k films in the back-end-of-line (BEOL)
- state-of-the-art immersion lithography to achieve competitive density and chip size
- a focus on quality analog models for the digital communications marketplace
- providing a platform for derivative technologies such as RF CMOS and embedded DRAM, or eDRAM
