Quietly announced last June, IBM's new CoreConnect technology promises to simplify the chip-design process. CoreConnect allows pieces of chip designs or "cores" from multiple sources to be plugged together more easily to create new chips. First used to create a new high-performance, PowerPC embedded microprocessor, CoreConnect since has been embraced as a standard by a number of chip designers. "It saves significant design and testing time," says Tom Collopy, licensing and alliances manager in the PowerPC development group at IBM. CoreConnect is known as an "on-chip bus" standard. A "bus" in computer terms is basically a communications link. In the past, different makers of chips created their own proprietary bus technologies, making their chip designs incompatible. The on-chip bus lets designers put together different pieces of chips to create new designs faster. In other words, in the automotive world this would be like letting Ford use a BMW engine if it wanted, while DaimlerChrysler could use a body design by Mazda. It makes designs much more compatible. The new de facto bus standard, for which IBM has openly published the specs and licensed the technology for free to other chip designers, appears to be catching on. Initially, six companies had agreed to license the technology, and eight more have signed on since then. Among them are Cadence Design, Mentor Graphics, Summit Design, Lexra, and Carnegie Mellon University. "Having an open standard that is free of any licensing fees or royalties is critical to gaining acceptance," Collopy adds. John Teresko, John Sheridan, Tim Stevens, Doug Bartholomew, Patricia Panchak, Tonya Vinas, Samuel Greengard, Kristin Ohlson, and Barbara Schmitz contributed to this article.